1. Field of the Invention
The present invention generally relates to the design and manufacture of integrated circuit devices and, more particularly, to the electrical stress testing of integrated circuit devices, especially those containing transistors of different types.
2. Description of the Prior Art
The change of electrical characteristics of electrical components due to thermal and electrical stress during use is well-recognized. In some applications, particularly involving semiconductor devices, therefore, it is a common practice to operate a device for a sufficient period of time to stabilize the electrical characteristics of the device or component before placing it in service. This process can often be accelerated by operation of the device or component under adverse conditions of elevated temperature and/or increased operating voltages. Such operation is commonly referred to as burn-in.
In semiconductor devices and integrated circuits, in particular, burn-in is especially useful since latent defects such as improperly formed conductors which could cause unexpected failure during field operation will often fail during burn-in. Also, further diffusion of impurities, given a predetermined distribution in portions of the device, could be redistributed under adverse thermal or electrical conditions to drastically alter the electrical characteristics or cause failure of the device.
This latter consideration has become of major importance as transistor sizes have been reduced in integrated circuit devices. This is particularly true of field-effect transistors (FET's as channel lengths have been reduced below one micron. However, as improvements in technology have reduced the sizes of individual elements in integrated circuits, the electrical conditions under which such elements are optimally operated have become more critical. The same is true for burn-in operation. For example, in integrated circuit devices containing both bipolar transistors and CMOS transistors, the bipolar transistors are often optimized for operation at 3.6 volts while CMOS FET's, commonly integrated on the same chip with such bipolar devices are optimized for operation at 2.5 volts due to channel length and gate oxide thickness constraints. Likewise, optimum burn-in voltages differ between the two technologies (e.g. bipolar and CMOS) due to breakdown considerations. For example, during burn-in, bipolar devices are preferably electrically stressed at up to 1.1 times the optimum operating voltage while CMOS FET's are preferably stressed at up to 1.5 times the optimum operating voltage. This difference is at least in part due to the difference in conduction phenomena between the two devices since conduction occurs across a junction in a bipolar device but not in FET's, where conduction is controlled by the extent of a depletion region within a junctionless channel.
Burn-in has virtually become an indispensable requirement in the manufacture of integrated circuits having highly miniaturized transistors in order to assure an acceptable level of reliability. Therefore, arrangements for conducting such burn-in and testing operations have become an integral part of the design of such integrated circuits. However, all such arrangements, to date, have imposed some requirement on device design or manufacturing process which is at least expensive or time-consuming or requires substantial structure to be fabricated integrally with the device which is not thereafter usable. For example, U.S. Pat. No. 5,030,908 to Miyoshi et al. uses an electron beam to place a charge on a predetermined area of an integrated circuit and discharge is observed over time to determine the electrical characteristics of the device. U.S. Pat. No. 4,821,238 to Tatematsu teaches the provision of an on-chip test pattern generator. U.S. Pat. No. 4,855,672 to Shreeve discloses the provision of on-chip test circuitry usable in combination with a continuous lead-frame structure in the form of a tape which allows a plurality of integrated circuits to be wound on reels and thermally stressed while being simultaneously tested. U.S. Pat. No. 4,967,146 to Morgan et al teaches the provision of grooves on a wafer which facilitates burn-in and location of contacts for testing and later disassembly of the wafer into individual chips.
Another approach involves the use of a separate burn-in power supply lead which is not thereafter used. This approach requires an additional power plane in the integrated circuit and/or module carrying the integrated circuit and a pin which is either floated (if the two normal operating voltages are provided on-chip from the same power supply) or tied to the Vcc power plane (if on-chip voltage conversion is not provided) during normal operation. This requires some modification of the physical and electrical environment in which the integrated circuit is to be used as well as significant additional structure within the integrated circuit device, itself U.S. Pat. No. 4,336,495 to Hapke teaches the provision of on-chip switching for the purpose of testing which involves the application of a voltage which is outside the normal operating range of the device, such as a voltage of opposite polarity to normal operating voltage, in order to avoid the provision of an additional module pin. However, such an approach is not applicable to either electrical stressing of the circuit or the selective provision of a particular burn-in supply voltage to selected transistors of an integrated circuit. Similarly, U.S. Pat. No. 4,625,129 to Ueno teaches on-chip power supply switching for the purpose of removing power from selected portions of an integrated circuit which is similarly inapplicable to the provision of separate burn-in power supply voltages. Horiguchi U.S. Pat. No. 4,944,688, presents a very detailed description of the design of a fixed reference voltage generating circuit and is exemplary of the complexities which may be encountered for powering large integrated circuits even in the case of voltage generators which are not switchable and do not provide burn-in voltage generation capability. Distribution of V.sub.L circuits among the memory cell arrays powered thereby is shown in FIG. 4 of Horiguchi et al. This approach increases overall power consumption and consumes additional chip space.
A BICMOS logic converter for the purpose of burn-in operation of a bipolar emitter coupled logic (ECL) circuit is taught in IBM Technical Disclosure Bulletin, Vol. 33, No. 10B, published in March 1991. The purpose of this circuit is to allow operability of the bipolar ECL circuit when V.sub.DD is raised under burn-in operation conditions. In this circuit, a field effect transistor is used to alter a load resistance of an amplifier circuit which receives an input from a reference voltage source. The change of load resistance boosts the gain of the amplifier and raises the output voltage swing.